// //**************************************************************************************// // DESIGN BY: Chris Washington (christopherwashington@hotmail.com) // // Andrew Puryear (apurear@ieee.com) // // // // // // TAMU - RAYTHEON DESIGN TEAM: // // Andrew Puryear // // Chris Washington // // Graham Booker // // Mike Neatherlin // // Paul Fuller // // // // HARDWARE MODULE I/O DESCRIPTIONS // // // //**************************************************************************************// ======================================================================================================== FPGASA Data_out - half of a complex number resulting from processing. [20-bit] The magnitude should be taken in software to determine the resuting frequency spectrum clk_out - clock signal sychronized with system clock. Only activated when data is being transmitted to the display bugger. xmt_error - asserted signal denotes transmission error on FPGASA side resulting from change in data during transmission. --------------------------------------------------------------------------------------- Data_in - input data from ADC [16-bit] sample_clk - input clock to decimation module synchronized to ADC clock sys_clk - clock input to control fft and output modules. Divided to generate fft_clk. rst_ - asynchronous, active-low reset ======================================================================================================== DECIMATION decimation_out_reg - data output at 1/32 of sample_clk (due to decimation) and [20-bit] latched to FIFO clk_32 - clock resulting from down-sampling by 32 in decimation module. Used as control for FIFO and to denote when the FIFO has a full data window for FFT processing. ---------------------------------------------------------------------------------------- decimation_in - same as Data_in in FPGASA [16-bit] sample_clk - same as sample_clk in FPGASA rst_ - same as samplePclk in FPGASA ======================================================================================================== FFT FFT_out - output from 4096pt complex FFT performed in four stages [4096x40-bit] to be applied to OUTPUT module for post processing and output to display buffer output_rdy - assertion signals that FFT_out is valid for latching --------------------------------------------------------------------------------------- FFT_in - input to FFT from FIFO. Although FIFO is a 8192x20-bit [4096x40-bit] buffer, the values being passed are combed into a 4096x40-bit form with successive values occupying the real [39:20] and imaginary [19:0] portions of the 40-bit register. fft_clk - clock proportional to sys_clk used to control FFT module. the register at the end of the module(FFT_HOLD) is updated on the falling edge while the entry regiser (FFT_ENTRY) is refreshed on the rising edge. This module takes 4 fft_clk cycles to complete. fft_enable - assertion enables the FFT module to operate while de-assertion will freeze the module in the event of input glitch or invalid FIFO. rst_ - same as rst_ in FPGASA ======================================================================================================== BUTTERFLY o - output resulting from 4096-point butterfly operation [4096x40-bit] --------------------------------------------------------------------------------------- i - input to be passed through a 4096-point butterfly operation [4096x40-bit] ======================================================================================================== FFT8pt xout0 - xout7 - 8 outputs from 8-point FFT (real[39:20], imag[19:0]) [40-bit] --------------------------------------------------------------------------------------- x0 - x7 - 8 inputs to 8-point FFT (real[39:20], imag[19:0]) [40-bit] ======================================================================================================== TWIDDLE o - new values resulting from twiddle factor multiplication [4096x40-bit] --------------------------------------------------------------------------------------- i - reordered points from BUTTERFLY module to be multiplied [4096x40-bit] by a twiddle factor corresponding to the current stage. Note that the twiddle factors originate in a data bank that must be hardwired or loaded during system reset. stage - used to determing the normalization factor and appropriate [2-bit] twiddle factor. Also used in FFT module to determine proper reorders before BUTTERFLY and TWIDDLE modules ======================================================================================================== OUTPUT data_out - same as Data_out in FPGASA (source in this module) [20-bit] clk_out - same as clk_out in FPGASA (controlled in this module) xmt_error - same as xmt_error in FPGASA --------------------------------------------------------------------------------------- FFT_OUTPUT_REG - data resulting from 4096-point FFT ready for post [4096x40-bit] processing and output to display buffer sys_clk - same as sys_clk in FPGASA rst_ - same as rst_ in FPGASA ======================================================================================================== POSTPROCESS out - output bus to be latched in OUTPUT module for tranmission [8192x40-bit] to display buffer data_rdy - assertion denotes data on out is valid xmt_error - same as xmt_error in FPGASA (generated here) --------------------------------------------------------------------------------------- in1,in2 - reordered points from FFT_OUT_REG to be processed for output [4096x40-bit] data_xmt - assertion denotes data transmission is in progress. Changes in the transmission source data during transmission will trigger xmt_error ======================================================================================================== PPTWIDDLE o - new values resulting from twiddle factor multiplication [4096x40-bit] --------------------------------------------------------------------------------------- i - reordered points from BUTTERFLY module to be multiplied [4096x40-bit] by a twiddle factor corresponding to the current stage. Note that the twiddle factors originate in a data bank that must be hardwired or loaded during system reset. ======================================================================================================== ALU32 sum - output resulting from 32-bit, 2's complement (+) or (-) [32-bit] --------------------------------------------------------------------------------------- in1,in2 - 2's complement inputs to be operated on [32-bit] cntl - 2's complement operation (1:-, 0:+) ======================================================================================================== cALU40 real_out - real result of operation [20-bit] imag_out - imag reslut of operation [20-bit] --------------------------------------------------------------------------------------- real_1, real_2 - real inputs to be operated on [20-bit] imag_1, imag_2 - imag inputs to be operated on [20-bit] cntl - complex operation (00: C1 + C2 01: C1 - C2) [2-bit] (10: C1 + j*C2 11: C1 - j*C2) ======================================================================================================== mult_expj real_out - real result of exponential multiplication [20-bit] imag_out - imag reslut of exponential multiplication [20-bit] --------------------------------------------------------------------------------------- real_in - real input to be multiplied by exponential [20-bit] imag_in - imag input to be multiplied by exponential [20-bit] cntl - multiplication mode ( 0: exp(-jPI/4), 1: exp(-j3PI/4)) ======================================================================================================== cmult out - result of complex multiplication (real[39:20], imag[19:0]) [40-bit] --------------------------------------------------------------------------------------- in1,in2 - complex inputs for multiplication (real[39:20],imag[19:0]) [40-bit] norm - normalization setting (1: 2^18, 0: 2^14) ========================================================================================================